Thermal Modeling

Thermal limits on fast charging cylindrical 18650 cells

Why internal temperature gradients, not peak surface temperature, are the real constraint on charge rate for cylindrical cells.

Abstract thermal gradient imagery representing heat limits in cylindrical battery cells

Pack engineers routinely monitor surface temperature as the primary thermal safety signal during fast charge. A thermistor on the cell can surface reads the temperature, the BMS compares it to a threshold, and charge current is stepped down or cut when that threshold is reached. This setup works. It catches gross overheating events. But it systematically underestimates what is happening at the jelly roll core, and that gap is exactly where the fastest degradation accumulates.

The geometry of a cylindrical 18650 cell makes the core-surface temperature difference a structural feature of how heat moves through the cell, not an edge case. Understanding that geometry is the starting point for setting charge rate limits that are actually grounded in thermal reality rather than inherited conservatism.

Heat generation and the radial path out

During charging, Joule heating occurs throughout the electrode stack: at the cathode, anode, and in the electrolyte between them. The heat source is distributed, not localized. For a cylindrical cell, that distributed source sits inside a rolled stack of materials with strongly anisotropic thermal conductivity.

Conductivity along the axis of the cell (axially, through the spiral cross-sections) is relatively high, around 20 to 40 W/m per Kelvin depending on the electrode formulation. Conductivity across the spiral layers, the radial direction toward the can surface, is much lower: in the range of 0.3 to 0.8 W/m per Kelvin for typical NMC/graphite cells. The electrode coating layers, separator, and electrolyte in the gaps all contribute low-conductivity resistance to radial heat transfer.

What this means is that heat generated at or near the core of the jelly roll has a difficult path to the outside. The can surface is where cooling happens (convection to air, or contact cooling in a thermally managed pack), so the steady-state gradient during fast charge runs from the hot core to the cooler can wall. That gradient is not a malfunction. It is the normal operating condition.

What the numbers look like at 2C

Consider a 2.2 Ah INR18650 cell being charged at 2C (4.4 A) from 20% to 80% SoC in a 30 degree Celsius ambient environment, without active cooling. In internal simulation work we have done with this cell format, the surface temperature peaks around 40 to 42 degrees Celsius at the end of the constant-current phase. The BMS sees this number and concludes the cell is operating within a safe envelope, which by datasheet standards it is.

The core temperature during that same period reaches 49 to 52 degrees Celsius in our model, depending on the exact heat generation profile during the CC phase. The 8 to 12 degree Celsius delta between core and surface is not recoverable by surface measurement alone. You need either a physical probe at the core (impractical in a production cell) or a thermal model that infers core temperature from surface measurement plus the known heat generation calculated from current and resistance estimates.

At 1C, the delta shrinks to roughly 3 to 5 degrees Celsius. That is why 1C or lower charge rates are the default recommendation for most cells without thermal management: the core-surface gap is small enough that surface monitoring provides a reasonable proxy for internal state. Push to 2C or above without adjusting your control logic and the proxy breaks down.

The two failure mechanisms that live in the gradient

The core-surface gradient is not just a measurement calibration problem. It creates two distinct electrochemical failure drivers that affect cell life in opposite temperature directions.

First, SEI layer growth on the anode accelerates at elevated temperature. The solid electrolyte interphase that forms on graphite anode particles during initial formation cycles continues to grow slowly throughout cell life, consuming lithium irreversibly and increasing cell resistance. This growth follows Arrhenius kinetics: the rate roughly doubles every 8 to 10 degrees Celsius. The hottest part of the cell, the core during high-rate charging, therefore sees the fastest SEI growth. Over hundreds of cycles, the core ages measurably faster than the surface-adjacent electrode layers.

Second, at the same time that the core is running hot, there is a physical interpretation of that gradient in terms of current distribution within the cell. The non-uniform temperature creates non-uniform local reaction rates, which means the lithium intercalation and de-intercalation process is not happening at the same pace across the entire electrode area. The slow-intercalation regions accumulate lithium concentration gradients that contribute to particle stress and potential lithium plating risk in specific operating windows.

These two mechanisms interact over time. As the core-adjacent electrode layers age faster, their impedance increases, which shifts heat generation even further toward the core, which accelerates core aging further. It is a self-reinforcing process. The cell does not fail suddenly; it drifts into an asymmetric aging state that shows up first as capacity fade and eventually as resistance-dominated power loss.

Why standard thermal cutoffs miss this

The standard protective approach is to set a surface temperature cutoff at 45 to 50 degrees Celsius and reduce charge current when that limit is approached. This is a reasonable engineering choice when you do not have a thermal model of the core. It provides a safety margin against gross overheating and prevents the most obvious surface-adjacent degradation accelerators.

The problem is that a surface cutoff at 45 degrees Celsius, combined with the gradient we described above, implies that charge is sometimes reduced at a point when the core is at 50 to 53 degrees Celsius. If you are using that cutoff to protect cycle life rather than just prevent a runaway event, you may be cutting charge current based on surface temperature reaching a threshold that was set for a different reason than core thermal protection. The surface threshold and the core thermal protection threshold are related by the gradient, and the gradient is a function of charge rate, SoC, cell age, and ambient temperature. It is not a fixed offset you can bake in as a constant.

We are not arguing that surface temperature monitoring is useless. It remains an important and necessary measurement. The point is that surface temperature alone is not sufficient to determine whether the core is within an acceptable thermal window, especially at fast-charge rates where the gradient is large and variable.

Building a model-informed threshold

The practical alternative is to run a thermal model alongside the BMS logic and use estimated core temperature rather than (or in addition to) measured surface temperature as the primary charge control input. The model needs to be parameterized with the specific cell's radial thermal conductivity, heat capacity, and heat generation as a function of current and SoC. These parameters can be extracted from controlled laboratory measurements: calorimetry for heat generation, laser flash analysis or transient hot wire for thermal conductivity.

Once the model is parameterized, it takes current, measured surface temperature, and ambient temperature as inputs, and it outputs an estimate of core temperature in real time. The charge protocol then operates against a core temperature limit rather than a surface temperature limit.

The benefit in charge speed terms: the core temperature limit is the actual physical constraint, so when the surface-to-core gradient is smaller (lower ambient, lower SoC, better pack cooling), the protocol can charge faster without violating the actual thermal limit. When the gradient is larger (high ambient, high SoC, poor pack cooling), the protocol backs off current earlier. The cutoff is calibrated to physical reality instead of a conservative proxy.

In the scenario we described earlier with a 2.2 Ah cell at 30 degrees Celsius ambient, a model-informed protocol can maintain 2C charge rate through roughly the first 40% of SoC before the predicted core temperature approaches the limit, then step down to 1.5C through the 40% to 70% window, then to 1C for the final approach. The surface-based protocol with a fixed 1C limit because of thermal conservatism would take significantly longer for the same result. The key is that the model-informed approach is making decisions based on the actual thermal state, not a temperature proxy with an implicit and unstated margin baked in.

The role of cell-to-cell variation

One aspect that complicates this in a real pack context is manufacturing variation. Two cells of the same part number can have meaningfully different thermal resistances, particularly in the first few hundred cycles as the electrode stack compresses and the internal contact resistances stabilize. Our parameterization approach accounts for this by identifying cell-specific parameters from early-cycle data rather than assuming all cells match the nominal datasheet values.

The practical implication for pack designers is that a thermal model built on nominal cell parameters will have a predictable bias. If the goal is to set a charging protocol that is safe for the worst-case cell in the pack, the model should be parameterized with conservative thermal resistance values (high radial resistance, lower effective conductivity) rather than central estimates. This preserves the safety margin while still allowing the protocol to be more adaptive than a fixed-current approach.

Getting the geometry right at the cell level is the foundation. The surface thermistor tells you something, but it cannot tell you what is happening eight or nine millimeters from the can wall at the center of the jelly roll where the heat is being generated. That requires a model, and that model needs to be coupled to the charge control logic to do any useful work.

Engineering Notes

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