State-of-charge estimation is one of the most developed areas in BMS algorithms, with a substantial body of academic work covering extended Kalman filters, unscented Kalman filters, adaptive observers, and neural-network-based estimators. The majority of that work is validated at C-rate conditions of 1C and below, which represent the range where the dominant error source is sensor noise and model parameter drift over cell age.
At 2C and above, a different set of error sources becomes dominant. The cell under high-rate charge is far from the equilibrium conditions that the open-circuit voltage curve assumes. Overpotentials are large, temperature rises quickly, and the relationship between terminal voltage and SoC becomes dependent on rate in ways that a standard OCV-based estimator cannot track without explicit rate and temperature compensation. The result is SoC estimates that drift significantly, particularly in the high-SoC region where the charge protocol needs accurate SoC information most urgently to prevent overcharge.
Why OCV-based estimation fails at high rates
Open-circuit voltage as a function of SoC is a thermodynamic property of the cell. The OCV curve maps the equilibrium electrode potential at each lithiation state. This is a useful relationship because it is relatively cell-invariant for a given chemistry and can be used to anchor a Coulomb-counting estimator when the cell is at rest or near rest.
The problem during fast charge is that the cell terminal voltage under load is not the OCV. It is the OCV plus the sum of all overpotential contributions: ohmic resistive drop, charge transfer overpotential at the anode and cathode interfaces, concentration overpotential from lithium concentration gradients in the electrolyte and electrode particles. At 2C in an 18650 cell, the total overpotential during charge can reach 80 to 150 mV depending on temperature and SoC. This pushes the terminal voltage well above the equilibrium OCV for the same actual SoC.
A purely OCV-based estimator that infers SoC from terminal voltage will consistently overestimate SoC during fast charge because it interprets the overpotential-inflated terminal voltage as corresponding to a higher SoC on the OCV curve. The error grows with increasing C-rate and decreases with temperature (because overpotential is lower at higher temperature). In practical terms: at 2C and 25 degrees Celsius, an OCV-only estimator may report 85% SoC when the cell is actually at 78%, and that error is largest in the 70 to 90% SoC region where the OCV curve is steep.
The interaction with cell temperature
Temperature complicates SoC estimation during fast charge in two separate ways. The first is the direct effect on overpotential: charge transfer resistance and electrolyte resistance both decrease with increasing temperature, so the same C-rate produces lower overpotential at 40 degrees Celsius than at 20 degrees Celsius. An estimator that does not account for temperature will produce errors of different magnitude and sign at different temperatures, even at the same C-rate.
The second complication is the interaction between temperature uncertainty and SoC uncertainty. Most BMS designs place thermistors on the outer surface of the cell or module. During fast charge, as discussed in earlier posts on this blog, there is a temperature gradient between the cell core and surface. The core temperature relevant to the electrochemical processes driving overpotential is higher than the surface temperature the thermistor reads. An estimator that uses the surface thermistor temperature to compensate its overpotential model is using a temperature value that is systematically low relative to the electrochemically-relevant internal temperature.
The compound effect: at 2C and 35 degrees Celsius ambient in an 18650 cell, with 6 to 10 degrees of core-to-surface temperature gradient, the estimator is operating with a temperature error of 6 to 10 degrees Celsius in its overpotential compensation model. That temperature error propagates into SoC estimation error of roughly 2 to 4% in the high-SoC region. This is not catastrophic, but for a tight charge protocol that terminates at 4.18V to limit high-SoC SEI growth, a 3% SoC overestimate means the cell may actually reach 4.21V before the protocol termination condition fires.
Coulomb counting as the fast-charge workhorse
For fast-charge conditions specifically, Coulomb counting with a well-calibrated current sensor is more reliable than OCV-based or voltage-model-based SoC estimation. The reason is that Coulomb counting integrates the actual charge delivered to the cell, which is the physically correct quantity during a known charge profile. The OCV-based approaches try to infer SoC from voltage observations corrupted by overpotential, which requires an accurate overpotential model that in turn requires accurate temperature knowledge.
Coulomb counting has its own error sources: current sensor offset and gain error, integrator drift over time, initial SoC uncertainty. These errors accumulate with time rather than being related to charge rate, so they are more manageable in a charge session of fixed duration than in a long discharge or mixed-cycle application. For a 45-minute fast-charge session with a well-calibrated current sensor (shunt-based, with drift below 0.5%), Coulomb counting SoC error at the end of the session is typically below 1.5% if the initial SoC is known.
The practical combination for a fast-charge BMS is: start each charge session with an OCV-based SoC anchor (with the cell at rest before charge begins, so the OCV is valid), then switch to Coulomb counting as the dominant estimator during the charge event. Use the voltage model and temperature state as consistency checks that flag anomalies (unexpected voltage deviation from expected trajectory at known SoC and temperature) rather than as primary estimation signals during charge.
Where the estimator actually matters for protocol control
Not all regions of the charge event are equally sensitive to SoC estimation accuracy. In the early charge phase (SoC 10 to 60%), the OCV curve has a relatively flat slope and the terminal voltage is far from the cutoff voltage. SoC estimation errors of 3 to 5% in this region have little practical consequence for protocol control because the charge is rate-limited, not SoC-limited.
The critical region is the high-SoC taper: roughly 75 to 100% SoC, where the constant-voltage phase is approached and the protocol transitions from constant current to voltage-limited. Here, SoC estimation error maps directly to charge cutoff error. An overestimate of SoC causes the protocol to taper prematurely (leaving capacity uncharged and reducing usable range). An underestimate delays tapering and risks cell overvoltage. The balance between these two errors depends on what matters more for the specific application: usable range (error in the underestimate direction is better) or cell protection (error in the overestimate direction is better).
For two-wheeler applications in India where range per charge is a primary user concern, the tendency in protocol design is to accept a slightly wider SoC estimation window before triggering taper rather than to cut off conservatively and leave range behind. The implication for the estimator is that it needs to be accurate and conservative in the 75 to 95% SoC region: do not overestimate SoC (which triggers premature taper), but be confident enough to not significantly underestimate (which delays taper and risks overcharge).
Temperature compensation as a first-order fix
The most practical improvement to a standard BMS SoC estimator for fast-charge accuracy is explicit temperature compensation of the overpotential model. This does not require a full physics-based electrochemical model. A simplified parameterization that captures the temperature sensitivity of the two dominant overpotential terms (ohmic resistance and charge transfer resistance) is usually sufficient.
The ohmic resistance temperature coefficient for a typical NMC/graphite 18650 cell is well-characterized in published literature and can be verified with a quick measurement at two temperatures. The charge transfer resistance temperature dependence requires fitting to measured impedance data but is stable over much of the cell's life (it drifts with SEI growth at high ages but is reasonable to hold fixed for early-life cells). A two-parameter overpotential model with temperature coefficients for each term captures most of the estimation improvement available from temperature compensation without requiring a full physics-based model.
The remaining accuracy gap after temperature compensation is due to the core-to-surface temperature error described above. Addressing that requires either a model-based core temperature estimate (not just surface thermistor reading) or an impedance-based internal temperature inference. Both of those require more investment but are the correct direction if the application requires tight high-SoC charge termination accuracy.